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RFP45N02L, RF1S45N02L, RF1S45N02LSM
May 1997
45A, 20V, 0.022 Ohm, N-Channel Logic Level Power MOSFETs
Description
The RFP45N02L, RF1S45N02L, and RF1S45N02LSM are N-Channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers and relay drivers. These transistors can be operated directly from integrated circuits. Formerly developmental type TA49243.
Features
* 45A, 20V * rDS(ON) = 0.022 * Temperature Compensating PSPICE Model * Can be Driven Directly from CMOS, NMOS, and TTL Circuits * Peak Current vs Pulse Width Curve * UIS Rating Curve * 175oC Operating Temperature
Ordering Information
PART NUMBER RFP45N02L RF1S45N02L RF1S45N02LSM PACKAGE TO-220AB TO-262AA TO-263AB BRAND FP45N02L F45N02L
Symbol
D
G
F45N02L
S
NOTE: When ordering, use the entire part number. Add the suffix, 9A, to obtain the TO-263AB variant in tape and reel, e.g. RF1S45N02LSM9A.
Packaging
JEDEC TO-220AB
SOURCE DRAIN GATE
JEDEC TO-262AA
SOURCE DRAIN GATE
DRAIN (FLANGE)
DRAIN (FLANGE)
A
JEDEC TO-263AB
M
A
A
DRAIN (FLANGE) GATE SOURCE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
4342
1
RFP45N02L, RF1S45N02L, RF1S45N02LSM
Absolute Maximum Ratings
TC = 25oC Unless Otherwise Specified RFP45N02L, RF1S45N02L, RF1S45N02LSM Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Derate Above 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG Soldering Temperature of Leads for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL 20 20 10 45 Refer to Peak Current Curve Refer to UIS Curve 90 0.606 -55 to 175 260 W W/oC
oC oC
UNITS V V V A
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V VGS = VDS, ID = 250A VDS = 20V, VGS = 0V VGS = 10V ID = 45A, VGS = 5V VDD = 15V, ID 45A, RL = 0.33, VGS = 5V, RGS = 5 TC = 25oC TC = 150oC MIN 20 1 VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDS = 15V, VGS = 0V, f = 1MHz VDD = 16V, ID 45A, RL = 0.35 TYP 15 160 20 20 50 30 1.5 1300 724 250 MAX 2 1 50 100 0.022 260 60 60 36 1.8 1.65 80 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF
oC/W oC/W
Drain to Source Breakdown Voltage Gate to Source Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(5) Qg(TH) CISS COSS CRSS RJC RJA
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS ISD = 45A ISD = 45A, dISD/dt = 100A/s MIN TYP MAX 1.5 125 UNITS V ns
2
RFP45N02L, RF1S45N02L, RF1S45N02LSM Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 TC , CASE TEMPERATURE (oC) 150 175 0 25 ID, DRAIN CURRENT (A) 50
40
30
20
10
50
75
100
125
150
175
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs TEMPERATURE DERATING
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
2 1 ZJC, NORMALIZED THERMAL IMPEDANCE 0.5 0.2 0.1 0.1 .05 .02 .01 SINGLE PULSE 0.01 10-5 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x RJC x ZJC + TC 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) PDM
10-4
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
TC = 25oC, TJ = MAX RATED IDM, PEAK CURRENT (A)
500 VGS = 10V VGS = 5V 100 FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I
ID, DRAIN CURRENT (A)
100 100s 1ms 10
= I25
175 - TC 150
10ms 100ms DC VDSS MAX = 20V 50
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION TC = 25oC 10 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101
OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 1
10 VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
3
RFP45N02L, RF1S45N02L, RF1S45N02LSM Typical Performance Curves (Continued)
200 IAS, AVALANCHE CURRENT (A) 100 ID, DRAIN CURRENT (A) STARTING TJ = 25oC 75 VGS = 4.5V 100 VGS = 10V VGS = 5V
10
STARTING TJ = 150oC
50
VGS = 4V
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1] 1 0.001 0.01 0.1 1 tAV , TIME IN AVALANCHE (ms) 10 100
25
VGS = 3.5V VGS = 3V PULSE DURATION = 250s, TC = 25oC
0
0
1
2
3
4
5
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
100 ID(ON), ON-STATE DRAIN CURRENT (A) VDD = 15V 100 175oC 75 25oC 50 rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m)
FIGURE 7. SATURATION CHARACTERISTICS
-55oC
75
ID = 15A 50
ID = 30A
ID = 45A
ID = 2A 25
25 PULSE TEST PULSE DURATION = 250s DUTY CYCLE = 0.5% MAX 0 0 1.5 3.0 4.5 6.0 VGS, GATE TO SOURCE VOLTAGE (V) 7.5
PULSE DURATION = 250s 0 2.5 3.0 3.5 4.0 4.5 5.0 VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
2.0 PULSE DURATION = 250s, VGS = 5V, ID = 45A NORMALIZED ON RESISTANCE
350 VDD = 15V, ID = 45A, RL = 0.333 300 tr SWITCHING TIME (ns) 250 200 150 tf 100 td(OFF) 50 td(ON) 0 0 30 20 40 10 RGS, GATE TO SOURCE RESISTANCE () 50
1.5
1.0
0.5
0 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 200
FIGURE 10. SWITCHING TIME AS A FUNCTION OF GATE RESISTANCE
FIGURE 11. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
4
RFP45N02L, RF1S45N02L, RF1S45N02LSM Typical Performance Curves (Continued)
2.0 VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE 1.5 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 2.0 ID = 250A
1.5
1.0
1.0
0.5
0.5
0 -80
-40
0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
200
0 -80
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
2500 VDS , DRAIN TO SOURCE VOLTAGE (V) VGS = 0V, f = 1MHz 2000 C, CAPACITANCE (pF)
20 VDD = BVDSS 15 VDD = BVDSS
5.00 VGS , GATE TO SOURCE VOLTAGE (V)
1500 CISS 1000 COSS 500 CRSS
RL = 0.44 IG(REF) = 0.5mA VGS = 5V PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS VDD = 0.75 BVDSS VDD = 0.50 BVDSS VDD = 0.25 BVDSS
3.75
10
2.50
5
1.25
0 0 5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V)
0
0
20 --------------------I G ( AC T )
I G ( REF )
t, TIME (s)
80 --------------------I G ( AC T )
I G ( REF )
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Application Notes AN7254 and AN7260. FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
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RFP45N02L, RF1S45N02L, RF1S45N02LSM Test Circuits and Waveforms
VDS tP IAS VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG +
BVDSS L VDS VDD
VDD
0V
IAS 0.01 tAV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
RG DUT
-
VDD 10% 90% 10%
VGS
VGS 10%
50% PULSE WIDTH
50%
FIGURE 18. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
VDS RL
VDD VDS
Qg(TOT)
VGS = 10V VGS
+
Qg(5) VDD VGS VGS = 1V 0 Qg(TH) IG(REF) 0 VGS = 5V
DUT IG(REF)
FIGURE 20. GATE CHARGE TEST CIRCUIT
FIGURE 21. GATE CHARGE WAVEFORMS
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RFP45N02L, RF1S45N02L, RF1S45N02LSM
Temperature Compensated PSPICE Model for the RFP45N02L, RF1S45N02L, RF1S45N02LSM
.SUBCKT RFP45N02L 2 1 3 ;
CA 12 8 2.55e-9 CB 15 14 2.64e-9 CIN 6 8 1.05e-9
DPLCAP
rev 11/22/94
DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 33.3 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 4.9e-9 LSOURCE 3 7 4.9e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 0.14e-3 RGATE 9 20 0.89 RIN 6 8 1e9 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RDSMOD 10.31e-3 RVTO 18 19 RVTOMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
S1A 12 S1B CA GATE 1
5
10 RSCL2 5 51 6 8 + VTO + 16 21 MOS1 RIN CIN 8 RSOURCE MOS2 RSCL1 + 51 DBREAK 11 EBREAK + 17 18
DRAIN 2 LDRAIN
ESG
ESCL 50 RDRAIN
DBODY
-
EVTO 20 + 18 8 LGATE RGATE 9 6
LSOURCE 7 3 SOURCE
S2A 13 8 14 13 13 + EGS 6 8 EDS 15 S2B CB + 5 8 14 IT RBREAK 17 18 RVTO 19 VBAT +
-
-
VBAT 8 19 DC 1 VTO 21 6 0.583 ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/176,6))} .MODEL DBDMOD D (IS = 3.61e-13 RS = 5.06e-3 TRS1 = 3.05e-3 TRS2 = 7.57e-6 CJO = 2.0e-9 TT = 2.18e-8) .MODEL DBKMOD D (RS = 1.66e-1 TRS1 = -2.97e-3 TRS2 = 7.57e-6) .MODEL DPLCAPMOD D (CJO = 1.25e-9 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 2.313 KP = 53.82 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 8.95e-4 TC2 = -1e-7) .MODEL RDSMOD RES (TC1 = 3.82e-3 TC2 = 1.17e-5) .MODEL RSCLMOD RES (TC1 = 2.03e-3 TC2 = 0.45e-5) .MODEL RVTOMOD RES (TC1 = -2.27e-3 TC2 = -5.75e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.82 VOFF= -2.82) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.82 VOFF= -4.82) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.67 VOFF= 2.33) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.33 VOFF= -2.67) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; written by William J. Hepp and C. Frank Wheatley.
7
RFP45N02L, RF1S45N02L, RF1S45N02LSM
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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